Analog.Analog, design ideas, circuits, Spice simulations.
|
On this page:
This is some CD4007 stuff!
The CMOS metal gate 4000 series of logic ICs has now been around for at least 50 years. The series is still useful enough that at least 5 major chip manufacturers make at least some of the complete series. (Even with other advanced technologies, we still need nails...) The series has some unique characteristics including super low power, a wide supply voltage range from 3V to up to 18V, high noise immunity, a wide temperature range, high radiation tolerance, a good selection of packages, and very low cost. On the other hand, they are not highly integrated and they are not for high speed uses. Some of these positive (and negative) characteristics make these parts perfect to use with low noise analog circuits.
An interesting member of the series is the 4007UB. It is called a Dual Complementary Pair with Inverter. It is a simple part consisting of 3 matched NFET / PFET pairs and is available in a 14 pin package. These are connected so that it is easy to make 3 inverters.
As of 2022, it is made by Texas Instruments as the CD4007UB, Nexperia as the HEF4007UB, and On Semiconductor as the MC14007UB. Up until recently, it was also made by ST Micro as the HCF4007UB so you might find some of those still around. With today’s multi-GHz, billion transistor IC’s I suppose it’s difficult to justify an IC that has just 6 transistors.
The 4007UB is a member of the original 4000 COSMOS series developed by RCA at the end of the 1960’s and the beginning of the 1970’s. Today’s CD4000 series can trace its lineage from RCA to GE to Intersil to Harris to TI. Most of the TI CD4000 data sheets are actually just updated scans of the original RCA data sheets. In the 1970’s, RCA also offered the CD4007UB as an analog part, calling it the CA3600 CMOS Transistor Array. Google “CA3600” and you will find its data sheet which contains lengthy application notes showing uses for it as an analog part.
In 1999, Bob Pease wrote an article about the 4007UB in Electronic Design magazine describing how its matched FET pairs could be used for interesting things. See What’s All This CD4007 Stuff, Anyhow?
A basic CMOS inverter is made from an NFET and a PFET. The input is connected to the NFET and PFET gates and the output is connected to the NFET and PFET drains. The NFET source and substrate are connected to VSS and the PFET source and substrate are connected to VDD. See the figure below.
The CMOS metal gate 4000 series of logic ICs has now been around for at least 50 years. The series is still useful enough that at least 5 major chip manufacturers make at least some of the complete series. (Even with other advanced technologies, we still need nails...) The series has some unique characteristics including super low power, a wide supply voltage range from 3V to up to 18V, high noise immunity, a wide temperature range, high radiation tolerance, a good selection of packages, and very low cost. On the other hand, they are not highly integrated and they are not for high speed uses. Some of these positive (and negative) characteristics make these parts perfect to use with low noise analog circuits.
An interesting member of the series is the 4007UB. It is called a Dual Complementary Pair with Inverter. It is a simple part consisting of 3 matched NFET / PFET pairs and is available in a 14 pin package. These are connected so that it is easy to make 3 inverters.
As of 2022, it is made by Texas Instruments as the CD4007UB, Nexperia as the HEF4007UB, and On Semiconductor as the MC14007UB. Up until recently, it was also made by ST Micro as the HCF4007UB so you might find some of those still around. With today’s multi-GHz, billion transistor IC’s I suppose it’s difficult to justify an IC that has just 6 transistors.
The 4007UB is a member of the original 4000 COSMOS series developed by RCA at the end of the 1960’s and the beginning of the 1970’s. Today’s CD4000 series can trace its lineage from RCA to GE to Intersil to Harris to TI. Most of the TI CD4000 data sheets are actually just updated scans of the original RCA data sheets. In the 1970’s, RCA also offered the CD4007UB as an analog part, calling it the CA3600 CMOS Transistor Array. Google “CA3600” and you will find its data sheet which contains lengthy application notes showing uses for it as an analog part.
In 1999, Bob Pease wrote an article about the 4007UB in Electronic Design magazine describing how its matched FET pairs could be used for interesting things. See What’s All This CD4007 Stuff, Anyhow?
A basic CMOS inverter is made from an NFET and a PFET. The input is connected to the NFET and PFET gates and the output is connected to the NFET and PFET drains. The NFET source and substrate are connected to VSS and the PFET source and substrate are connected to VDD. See the figure below.
The 4007UB has 3 such NFET / PFET pairs. See the figure below for its pin out.
As you can see, it is easy to connect the complementary pairs as three separate inverters.
In the 4007UB, the 3 NFET substrates are all connected to VSS and the 3 PFET substrates are all connected to VCC. The VSS pin 7 must always be connected to the most negative voltage and the VCC pin 14 must always be connected to the most positive voltage in your circuit. Be sure to consult the TI, Nexperia, or OnSemi data sheets for more information on their min/max voltages, speeds, current capabilities, etc. You can also find descriptions of their input and output protection structures. It is like 3 inverters of the more well known 4069UB but with more of the internal nodes connected to its pins.
Since some of the complementary pairs have their sources and substrates on separate pins, you can connect the FETs in many interesting and useful ways. This article will catalog the wide variety of analog and digital circuits that you can build using this simple part. Some of the application circuits shown here are adapted from the various manufacturer’s 4007UB data sheets, some are from the original RCA CA3600 data sheet, and finally, some are my designs.
Various Inverters:
In the 4007UB, the 3 NFET substrates are all connected to VSS and the 3 PFET substrates are all connected to VCC. The VSS pin 7 must always be connected to the most negative voltage and the VCC pin 14 must always be connected to the most positive voltage in your circuit. Be sure to consult the TI, Nexperia, or OnSemi data sheets for more information on their min/max voltages, speeds, current capabilities, etc. You can also find descriptions of their input and output protection structures. It is like 3 inverters of the more well known 4069UB but with more of the internal nodes connected to its pins.
Since some of the complementary pairs have their sources and substrates on separate pins, you can connect the FETs in many interesting and useful ways. This article will catalog the wide variety of analog and digital circuits that you can build using this simple part. Some of the application circuits shown here are adapted from the various manufacturer’s 4007UB data sheets, some are from the original RCA CA3600 data sheet, and finally, some are my designs.
Various Inverters:
Schmitt triggers:
Use resistors in the range of 50k to 1M for Rs and Rf below.
Use resistors in the range of 50k to 1M for Rs and Rf below.
Gates:
Tri-state:
These tri-state circuits need additional inverters either from a second 4007UB or from a 4069UB.
These tri-state circuits need additional inverters either from a second 4007UB or from a 4069UB.
Analog switch:
This next circuit has performance similar to one section of the 4016 analog switch.
This next circuit has performance similar to one section of the 4016 analog switch.
Analog current mirrors:
Class A Bias:
Putting a resistor around the basic inverter from the output to the input biases the two FETs into class A operation. If the two FETs have equal resistances, then the output and input become biased to the midway point between VDD and VSS. In reality, the P and N FETs are not identical, so the bias point is never quite at midway but it is typically close. This test circuit will show the bias point. Examining figure 7 of the TI CD4007UB data sheet shows that this configuration draws about 0.5 mA at +5V, 3.5 mA at 10V and 10.5 mA at 15V. Similarly, examining figure 5 of the Nexperia HEF4007UB data sheet shows about 3 mA at 5V, 7.7 mA at 10V and 19 mA at 15V. So there is a bit of variation from vendor to vendor.
Putting a resistor around the basic inverter from the output to the input biases the two FETs into class A operation. If the two FETs have equal resistances, then the output and input become biased to the midway point between VDD and VSS. In reality, the P and N FETs are not identical, so the bias point is never quite at midway but it is typically close. This test circuit will show the bias point. Examining figure 7 of the TI CD4007UB data sheet shows that this configuration draws about 0.5 mA at +5V, 3.5 mA at 10V and 10.5 mA at 15V. Similarly, examining figure 5 of the Nexperia HEF4007UB data sheet shows about 3 mA at 5V, 7.7 mA at 10V and 19 mA at 15V. So there is a bit of variation from vendor to vendor.
AC inverting amplifiers:
Using the class A bias with an input resistor results in a linear inverting amplifier that will work well to about 100 KHz. The gain equation is Av = - Rf / Rin Because of the class A self biasing, this amplifier needs to be AC coupled at its input and output. My experience is that these amplifiers have their best linearity over the range of VCC = +5V to +15V when the output voltage is limited to no more than about 2Vpp max. Three of these may be cascaded for super high gain.
Using the class A bias with an input resistor results in a linear inverting amplifier that will work well to about 100 KHz. The gain equation is Av = - Rf / Rin Because of the class A self biasing, this amplifier needs to be AC coupled at its input and output. My experience is that these amplifiers have their best linearity over the range of VCC = +5V to +15V when the output voltage is limited to no more than about 2Vpp max. Three of these may be cascaded for super high gain.
In regard to the discussion above about the class A current draw, if three of these amplifiers are used at the higher supply voltages, it could be that the part may start to draw a lot of current. For example based on the information in the Nexperia data sheet, three of these amplifiers could draw a total of about 57 mA at +15V. This is 855 mW which is greater than the device package power dissipation limit. Two of the FET pairs have separate connections for their sources. Resistors can be placed in series with these sources to limit the overall DC current flow through the inverter. These are then bypassed with capacitors. This technique does limit the current drive capability and reduces the FET gains which somewhat limit the AC signal output voltage. You may need to experiment with different source resistor values, but this is the general idea. When using the series resistors, make sure that pin 14 is connected to VCC and pin 7 is connected to ground (or VSS) as shown in the circuit below.
Low power logic level booster:
A battery powered bio-impedance measurement system needed a low power 2 phase carrier frequency driver. This circuit will boost a 3.3V 32.768 KHz square wave signal to 10 Vpp at very low power. It uses AC bypassed resistors on the sources of the first stage FETs just like the previous AC amplifier circuit. In this case here, this circuit draws between 120 uA and 380 uA (depending on the 4007UB brand). If the 10K source resistors (R3 and R4) are jumpered, this circuit draws between about 1.7 mA and 3 mA. Thus the resistors reduce the current draw about 10:1. Other attemps using 4069UB drivers also drew about 2.5 mA and 3.2 mA, and using LMC6482 op amps drew about 1.4 mA.
A battery powered bio-impedance measurement system needed a low power 2 phase carrier frequency driver. This circuit will boost a 3.3V 32.768 KHz square wave signal to 10 Vpp at very low power. It uses AC bypassed resistors on the sources of the first stage FETs just like the previous AC amplifier circuit. In this case here, this circuit draws between 120 uA and 380 uA (depending on the 4007UB brand). If the 10K source resistors (R3 and R4) are jumpered, this circuit draws between about 1.7 mA and 3 mA. Thus the resistors reduce the current draw about 10:1. Other attemps using 4069UB drivers also drew about 2.5 mA and 3.2 mA, and using LMC6482 op amps drew about 1.4 mA.
Differential amplifier:
A single 4007UB can make a differential amplifier called a CSDA.
A single 4007UB can make a differential amplifier called a CSDA.
Op amp:
Adding a high gain complementary inverting amplifier turns the CSDA into an operational amplifier. Note that IN+ and IN- of the op amp are reversed from the plain CSDA above because of the extra inversion from the output stage. You could get higher current drive by paralleling the other two sections of U2 but you may have to adjust the value of the compensation capacitor C1.
This circuit is essentially the same as the one described in this EDN article that uses the 4069UB. Note that the 4069UB pins shown on the schematic in that article are incorrect. The 4069UB is a 14 pin part and the schematic shows pin 15 in several places and ground on pin 8, both of which are wrong. That 4069UB based design uses 4 ICs while this equivalent 4007UB based design shown here only uses 2 ICs. As mentioned, the EDN circuit MUST use the 4069UB and NOT the 4049B.
Adding a high gain complementary inverting amplifier turns the CSDA into an operational amplifier. Note that IN+ and IN- of the op amp are reversed from the plain CSDA above because of the extra inversion from the output stage. You could get higher current drive by paralleling the other two sections of U2 but you may have to adjust the value of the compensation capacitor C1.
This circuit is essentially the same as the one described in this EDN article that uses the 4069UB. Note that the 4069UB pins shown on the schematic in that article are incorrect. The 4069UB is a 14 pin part and the schematic shows pin 15 in several places and ground on pin 8, both of which are wrong. That 4069UB based design uses 4 ICs while this equivalent 4007UB based design shown here only uses 2 ICs. As mentioned, the EDN circuit MUST use the 4069UB and NOT the 4049B.
Voltage controlled resistor:
Most VCR circuits including the one here are tricky to use because they rely on the physical properties of the controlled device(s). These properties are usually not well characterized and can have 2:1 or 3:1 manufacturing tolerance variations from batch to batch or vendor to vendor. This means you may have to tweak the control voltage ranges for example. I may cover other VCR architectures in another article at some point.
Most VCR circuits including the one here are tricky to use because they rely on the physical properties of the controlled device(s). These properties are usually not well characterized and can have 2:1 or 3:1 manufacturing tolerance variations from batch to batch or vendor to vendor. This means you may have to tweak the control voltage ranges for example. I may cover other VCR architectures in another article at some point.
Crystal Oscillator:
The resistors and capacitors shown are for use with a 32.768 KHz watch type crystal. Consult the TI and Nexperia data sheets for the R and C values for low MHz frequencies.
The resistors and capacitors shown are for use with a 32.768 KHz watch type crystal. Consult the TI and Nexperia data sheets for the R and C values for low MHz frequencies.
3 Phase RC Ring Oscillator:
The oscillator's frequency is approximate and varies a bit with power supply voltage from +4V to +15V. The resistor R can be between about 2.2K and at least 1M. In the frequency equation, C is in Farads so you would use 0.1 X 10E-6 for 0.1uF for example. Due to differences between the P and N FETs, the three "square" wave phases are not perfectly symmetrical.
The oscillator's frequency is approximate and varies a bit with power supply voltage from +4V to +15V. The resistor R can be between about 2.2K and at least 1M. In the frequency equation, C is in Farads so you would use 0.1 X 10E-6 for 0.1uF for example. Due to differences between the P and N FETs, the three "square" wave phases are not perfectly symmetrical.
Conclusions:
So what good is all of this you may ask? Except for a few unique circuits, you could buy most of the functionality I describe with higher integration, in smaller packages, or faster speeds.
I offer several reasons:
1) These circuits are cheap. Currently 4007UB’s are about $0.50 in small quantities and less than $0.10 to $0.15 in large quantities at Digikey or Mouser.
2) For an IC with 6 transistors, the 4007UB is amazingly versatile.
3) You can learn a lot about how CMOS circuits work by playing around with these circuits.
4) Spice models were available from NXP for the 4069UB inverter. This model actually characterizes the individual PFET and NFET devices and is not a simple behavioral model. Assuming that the Spice circuits for the PFET and NFET in the 4069UB are essentially the same as those for the 4007UB, you can extract the individual CMOS NFET and PFET models into separate files and symbols. Then you can build Spice simulations of all of the above circuits. I have put together some gates, an inverter, the tri-state buffer, and the analog switch into circuit symbols that can be used with the Tina-TI simulation program. I have also made a D flip-flop that can be used with Tina-TI. This lets you add some simple digital control capability to Spice simulations in Tina-TI. My experience is that the Spice versions seem to over estimate the packaging capacitance and actual circuits sometimes work faster than the modeled version. These models will be available elsewhere on ElectroLuck.net.
Final note: Most of the circuits presented here can also be built using the Advanced Linear Devices ALD1105 and ALD1115 parts. The ALD1105 has two complementary matched pairs in a 14 pin package. They might be more flexible than the 4007UB because all 4 gates, 4 drains, and 4 sources are brought out separately. The PFET substrates are pinned together and the NFET substrates are pinned together and should be connected to the most positive and most negative voltages respectively in your circuit. The ALD1115 is similar, but has one matched pair in an 8 pin package. These parts are limited to 12V maximum between the PFET and NFET substrates. They also cost a good deal more than the 4007UB.
Have fun!
11-November-2019, last edited 8-May-2022
So what good is all of this you may ask? Except for a few unique circuits, you could buy most of the functionality I describe with higher integration, in smaller packages, or faster speeds.
I offer several reasons:
1) These circuits are cheap. Currently 4007UB’s are about $0.50 in small quantities and less than $0.10 to $0.15 in large quantities at Digikey or Mouser.
2) For an IC with 6 transistors, the 4007UB is amazingly versatile.
3) You can learn a lot about how CMOS circuits work by playing around with these circuits.
4) Spice models were available from NXP for the 4069UB inverter. This model actually characterizes the individual PFET and NFET devices and is not a simple behavioral model. Assuming that the Spice circuits for the PFET and NFET in the 4069UB are essentially the same as those for the 4007UB, you can extract the individual CMOS NFET and PFET models into separate files and symbols. Then you can build Spice simulations of all of the above circuits. I have put together some gates, an inverter, the tri-state buffer, and the analog switch into circuit symbols that can be used with the Tina-TI simulation program. I have also made a D flip-flop that can be used with Tina-TI. This lets you add some simple digital control capability to Spice simulations in Tina-TI. My experience is that the Spice versions seem to over estimate the packaging capacitance and actual circuits sometimes work faster than the modeled version. These models will be available elsewhere on ElectroLuck.net.
Final note: Most of the circuits presented here can also be built using the Advanced Linear Devices ALD1105 and ALD1115 parts. The ALD1105 has two complementary matched pairs in a 14 pin package. They might be more flexible than the 4007UB because all 4 gates, 4 drains, and 4 sources are brought out separately. The PFET substrates are pinned together and the NFET substrates are pinned together and should be connected to the most positive and most negative voltages respectively in your circuit. The ALD1115 is similar, but has one matched pair in an 8 pin package. These parts are limited to 12V maximum between the PFET and NFET substrates. They also cost a good deal more than the 4007UB.
Have fun!
11-November-2019, last edited 8-May-2022
Spicy stuff with Tina-TI
Coming soon!
Coming soon!
How to measure capacitance with a function generator, a resistor, and a scope
Sometimes it is useful to be able to accurately measure the capacitance of things other than capacitors. And sometimes it is useful to be able to accurately measure the capacitance of an unmarked capacitor. Here’s an easy way.
In an electrical system, the time constant T is a way to characterize the response to a step input. The time constant of the response of a system to a rising step edge is the time it takes for the response to reach 1 – 1/e which is about 63.2% of the step size. In an RC circuit, t = RC, with t in seconds, R in ohms, and C in farads ie. 1 second = 1 ohm / 1 farad.
To measure C, we just need to rearrange this equation C = t / R. If we choose the right scaling values, we can make this easy to measure with a function generator, a resistor, and a scope.
1) Set the function generator:
Sometimes it is useful to be able to accurately measure the capacitance of things other than capacitors. And sometimes it is useful to be able to accurately measure the capacitance of an unmarked capacitor. Here’s an easy way.
In an electrical system, the time constant T is a way to characterize the response to a step input. The time constant of the response of a system to a rising step edge is the time it takes for the response to reach 1 – 1/e which is about 63.2% of the step size. In an RC circuit, t = RC, with t in seconds, R in ohms, and C in farads ie. 1 second = 1 ohm / 1 farad.
To measure C, we just need to rearrange this equation C = t / R. If we choose the right scaling values, we can make this easy to measure with a function generator, a resistor, and a scope.
1) Set the function generator:
- Output square wave.
- Frequency 100 Hz.
- 50 ohm termination off (if possible).
- Amplitude 10 Vpeak-peak
2: Add a resistor:
- Put a 10K resistor in series with the FG output such that you can measure the voltage on both sides of it.
3) Set the scope:
- Channel A on the direct output of the function generator.
- Channel B on the other side of the 10K resistor.
- Channels A and B vertical set so that 10 Vpp is maximized on screen, probably 2 V/division.
- Normal trigger on Channel A, rising edge.
- Set trigger level as low as possible while still getting a trigger.
4) Measure the scope probe capacitance:
- To measure capacitance in the lower pF range, start with the horizontal set to 100 nS/division.
- Triggering on Channel A, adjust so that the trigger position is near the left edge of the screen.
- You should see the step edge on A and a slower rising signal on B.
- Vertically align the lower left A and B scope traces.
- Measure the time from the Channel A step edge to the point on the slower rising edge on Channel B where it reaches 6.32 V.
- If the time delay measurement is in nSec, multiply by 0.1 and if it is in uSec, multiply by 100.
- This value is the capacitance of the scope probe on Channel B in picofarads (pF). Assuming you are using 10:1 probes, it will probably be somewhere between 5 pF and 25 pF. Record this value.
|
|
5) Add the device under test (DUT):
- Again measure the time delay from the channel A step edge to the point on the slower rising edge on Channel B where it reaches 6.32 V. If the capacitance is larger than a few 100 pF, you may need to adjust the scope's horizontal scale. To get the capacitance in pF, if the measured time delay t as shown above is in nSec, multiply by 0.1, if in uSec, multiply by 100, and if in mSec, multiply by 100000.
- Record this value. This measurement is the sum of the capacitance of the scope probe plus the capacitance of the DUT in picofarads.
6) Compute the capacitance of the DUT:
7) Note:
- Subtract the scope probe capacitance from the total capacitance.
- Cdut = Ctotal - Cprobe
- With an accurate 10K resistor and with care, the method can be surprisingly accurate.
7) Note:
- This method is easy once you get the hang of it.
- If your DUT has more capacitance than a few hundred pF, you will need to adjust the scope horizontal accordingly.
- Just remember that the time measurement accuracy of your scope will probably diminish.
- A similar complementary method can be used to measure inductors, TBD.
Some example measurements:
My scope probe set to 10X: |
16.1 pF |
A ceramic capacitor marked 330: |
32.4 pF |
50 ohm RF coaxial cable, 5.85 feet (1.778 m) length: |
122.5 pF 21 pF/foot 69 pF/m |
RG59B/U 75 ohm video coaxial cable, 6 feet (1.829 M) length: (Data sheet says RG59B/U is nominally 20.5 pF/foot) |
133.1 pF 22 pF/foot 72.8 pF/m |
Belkin CAT-5e cable, between the orange and orange white wires of a twisted pair (differential), 14 feet (4.267 m) length: |
231.9 pF 16.6 pF/foot 54.4 pF/m |
Belkin Cat-5e cable, between the orange/orange white pair connected together and the green/green white pair connected together (common mode), 14 feet (4.267 m) length: |
217.9 pF 15.5 pF/foot 51.1 pF/m |
A large 8 layer 400 mm x 366 mm unpopulated PCB, between the power plane and ground plane: The PCB is 1.6 mm thick FR-4 with the layer stack up (as I recall) as follows, top / plane / tr1 / tr2 / tr3 / tr4 / plane / bottom. Plane to plane spacing is probably about 0.046” (1.17 mm). Board area is 227 inch^2 (1464 cm^2). Interestingly, my measurements are about 15X what most PCB calculators say the capacitance should be. I need to check the layer stack. |
70584 pF 0.071 uF 311 pF/inch^2 48 pF/cm^2 |
Between one of my hands and the other to scope ground: This was very dependent on how hard I pushed on the connections. The IEC 60601 safety standards use 220 pF typical for this value. |
approximately 280 pF |
PVC zip cord, 16 AWG, 5.92 feet (1.8 m) length: |
95 pF 18.3 pF/foot 52.8 pF/m |
My scope probe set to 1X: This is why 10X probes are better for any kind of high speed work. |
101 pF |
8-May-2022
How to drive higher power from a processor or FPGA/CPLD pin
Most microcontrollers and virtually all FPGA’s and CPLD’s have GPIO pins that output voltages of +3.3V or lower. Older microcontrollers (PIC16, AVR) have 5V output pins. This means that external circuits must be used to drive external devices with any kind of power. This page illustrates some typical circuits that can overcome this challenge.
Essentially the drive problem is one of controlling current through a load. The load presents itself as some kind of resistance or impedance. If you put a higher voltage at one end of the load and a lower voltage at the other end, current will flow through the load in one direction. For the purposes of this note, we will use “ground” as the lower voltage. Current and thus power to the load can be controlled with a switch. Close the switch and current will flow delivering power to the load. Open the switch and current will be interrupted, removing power from the load. You can put the switch on either side of the load.
When the switch is placed between the load and ground, the load is said to be controlled with a “low side switch”. The other side of the load is connected to the positive voltage source. Close the switch and current flows through the load and the switch to ground. See the illustration below.
Most microcontrollers and virtually all FPGA’s and CPLD’s have GPIO pins that output voltages of +3.3V or lower. Older microcontrollers (PIC16, AVR) have 5V output pins. This means that external circuits must be used to drive external devices with any kind of power. This page illustrates some typical circuits that can overcome this challenge.
Essentially the drive problem is one of controlling current through a load. The load presents itself as some kind of resistance or impedance. If you put a higher voltage at one end of the load and a lower voltage at the other end, current will flow through the load in one direction. For the purposes of this note, we will use “ground” as the lower voltage. Current and thus power to the load can be controlled with a switch. Close the switch and current will flow delivering power to the load. Open the switch and current will be interrupted, removing power from the load. You can put the switch on either side of the load.
When the switch is placed between the load and ground, the load is said to be controlled with a “low side switch”. The other side of the load is connected to the positive voltage source. Close the switch and current flows through the load and the switch to ground. See the illustration below.
When the switch is placed between the positive voltage and the load, the load is said to be controlled with a “high side switch”. The other side of the load is connected to ground. Close the switch and current flows through the switch and the load to ground. See the illustration below.
There are various reasons why you may want to use one configuration or the other. For several reasons, low side switching is easier to implement, primarily because the emitter of the NPN or the source of the NMOS that is being used as the controlled switch are at the same ground potential as the processor, FPGA, or CPLD. The top side of the load must be connected to V+. This may not be a problem when everything is located on a PCB. But if the load is remote from the switch, you will need to run two wires, one from the switch and one to V+. This could create a safety hazard. In many industrial settings, high side switching may be more practical and safe because the load could be returned to any convenient ground. Even if a local ground is not available and a second wire is needed, the wire will be safer in fault conditions because it has the ground potential on it rather than a (possibly high) voltage. Another use of high side switching is to selectively control the power rails to certain subsections of your circuit while keeping a common ground reference.
The illustration below shows various typical load devices including resistors, lamps, LEDs, strings of LEDs, heater elements, relay coils, solenoid coils, DC brush motors, and audio buzzers. Notice that I show a diode in parallel when the load is inductive. You may also need to put a snubber circuit consisting of a resistor in series with a capacitor in parallel with very inductive or noisy loads. For this article, I use a generic box to represent any of these specific load devices.
The illustration below shows various typical load devices including resistors, lamps, LEDs, strings of LEDs, heater elements, relay coils, solenoid coils, DC brush motors, and audio buzzers. Notice that I show a diode in parallel when the load is inductive. You may also need to put a snubber circuit consisting of a resistor in series with a capacitor in parallel with very inductive or noisy loads. For this article, I use a generic box to represent any of these specific load devices.
As mentioned above, a typical microcontroller, FPGA, or CPLD GPIO (I’ll use PLD generically to refer to FPGA’s or CPLD’s) pin does not have enough current drive or sufficient voltage to drive most typical load impedances. The mechanical switches in the illustrations above are obviously not that useful for control with a microcontroller or PLD. Therefore, transistors or MOSFETs are used as controlled switches. Virtually all PLD’s and some microcontrollers have separate voltage supply rails for their internal logic and for their I/O pins. The I/O pins are powered by a pin or pins usually called VCCIO or something similar. Larger FPGAs can have several groups of GPIO, each powered by a different VCCIO pin. Even if the part is internally using a low voltage like +1.8V or +2.2V for example, you should try to power the GPIO pins that you are using to drive your power device with +3.3V.
Please be aware that the examples presented here are just for guidance, you will have to prototype and test the design in your circuit to be sure that it works correctly in all situations. Additionally, these circuits are mostly intended only for simple on and off control of DC power to a load. They are generally not intended for high speed (greater than a few kHz or so) pulse width modulated (PWM) control. MOSFETs, especially the high power, low gate drive voltage varieties have a very high capacitance between the gate and the source that can be difficult to drive at high speed. If you need to PWM the current to your load at high speed with high power, please consult the websites of the various semiconductor manufacturers such as TI, Nexperia, OnSemi, ST Micro, Analog Devices, and others for these specialized parts. Look for “gate drivers”. These parts are designed to supply the necessary current for rapidly charging and discharging the MOSFET’s gate capacitance. If you need bidirectional control of power to the load for example to spin a DC motor in both directions, consult these same manufacturers or Monolithic Power Systems for half bridge and full bridge gate drivers. If you need to control an AC current like mains, you could either use one of the circuits here to drive an electromechanical relay to switch the AC or you could use a solid state relay.
Low Side Driver Circuits
L1) Simple NPN transistor low side drive
This circuit is suitable for driving a small signal NPN switching transistor. In this circuit, the transistor is called a saturated switch. Output a 0 from the GPIO and the load is off, output a 1 and the transistor is on and the load is powered on.
Find the resistance/impedance of the load, then find the current through the load at the circuit V+ as follows:
IMAX = V+max / RLoad
Say for example that the load is a Panasonic TX2-12V signal relay and say that we have specified a 2N3904 NPN transistor. The relay data sheet says that its coil voltage is 12V and its resistance is 1028 ohms. Imax = 12/1028 = 0.012A. We need to determine the value of the base resistor R in the schematic below. The 2N3904 data sheet indicates that B (beta), the transistor common emitter current gain is 10. The base current is then
IB = Imax / B
So in our example IB = 0.012 / 10 = 0.0012A. Any mocrocontroller or PLD can output this current.
Then RB = (VIN – VBE) / IB
VIN is the microcontroller or PLD’s GPIO voltage. Say for our example that it is +3.3V. From the 2N3904 datasheet, the VBE saturation voltage is 0.85V at a 10mA collector current. This is close enough to our coil current, so we will use that value. We get RB = (3.3 – 0.85) / 0.0012 = 2042 ohms. Let’s use a 2.0K resistor for R in the schematic.
Let’s check that the transistor can support this load. The power dissipation in the transistor when it is on is
PD = VCEsat IMAX
From the 2N3904 data sheet, VCEsat is 0.85V at 10mA and 0.95V at 50mA. Let’s use 0.95V as a worst case.
So PD = (0.95) * (0.012) = 0.0114W = 11.4mW.
From the 2N3904 data sheet, the SOT23 package version has a thermal resistance, junction to ambient of 357C/W. So this part will rise 357 * 0.0114 = 4 degrees C. This design is safe.
Please be aware that the examples presented here are just for guidance, you will have to prototype and test the design in your circuit to be sure that it works correctly in all situations. Additionally, these circuits are mostly intended only for simple on and off control of DC power to a load. They are generally not intended for high speed (greater than a few kHz or so) pulse width modulated (PWM) control. MOSFETs, especially the high power, low gate drive voltage varieties have a very high capacitance between the gate and the source that can be difficult to drive at high speed. If you need to PWM the current to your load at high speed with high power, please consult the websites of the various semiconductor manufacturers such as TI, Nexperia, OnSemi, ST Micro, Analog Devices, and others for these specialized parts. Look for “gate drivers”. These parts are designed to supply the necessary current for rapidly charging and discharging the MOSFET’s gate capacitance. If you need bidirectional control of power to the load for example to spin a DC motor in both directions, consult these same manufacturers or Monolithic Power Systems for half bridge and full bridge gate drivers. If you need to control an AC current like mains, you could either use one of the circuits here to drive an electromechanical relay to switch the AC or you could use a solid state relay.
Low Side Driver Circuits
L1) Simple NPN transistor low side drive
This circuit is suitable for driving a small signal NPN switching transistor. In this circuit, the transistor is called a saturated switch. Output a 0 from the GPIO and the load is off, output a 1 and the transistor is on and the load is powered on.
Find the resistance/impedance of the load, then find the current through the load at the circuit V+ as follows:
IMAX = V+max / RLoad
Say for example that the load is a Panasonic TX2-12V signal relay and say that we have specified a 2N3904 NPN transistor. The relay data sheet says that its coil voltage is 12V and its resistance is 1028 ohms. Imax = 12/1028 = 0.012A. We need to determine the value of the base resistor R in the schematic below. The 2N3904 data sheet indicates that B (beta), the transistor common emitter current gain is 10. The base current is then
IB = Imax / B
So in our example IB = 0.012 / 10 = 0.0012A. Any mocrocontroller or PLD can output this current.
Then RB = (VIN – VBE) / IB
VIN is the microcontroller or PLD’s GPIO voltage. Say for our example that it is +3.3V. From the 2N3904 datasheet, the VBE saturation voltage is 0.85V at a 10mA collector current. This is close enough to our coil current, so we will use that value. We get RB = (3.3 – 0.85) / 0.0012 = 2042 ohms. Let’s use a 2.0K resistor for R in the schematic.
Let’s check that the transistor can support this load. The power dissipation in the transistor when it is on is
PD = VCEsat IMAX
From the 2N3904 data sheet, VCEsat is 0.85V at 10mA and 0.95V at 50mA. Let’s use 0.95V as a worst case.
So PD = (0.95) * (0.012) = 0.0114W = 11.4mW.
From the 2N3904 data sheet, the SOT23 package version has a thermal resistance, junction to ambient of 357C/W. So this part will rise 357 * 0.0114 = 4 degrees C. This design is safe.
L2) Simple NMOS FET low side drive
This circuit is suitable for driving a small signal NMOS FET switch. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on. This circuit should use a type of NMOS that most manufacturer’s informally call “logic level” where the device can be fully switched on with a voltage less than +5V. This means that the gate voltage necessary to drive the drain to source into the full on state is compatible with typical logic parts. In the figure, an OnSemi BSS138K is suggested. Note the K suffix, other versions of the BSS138 are not logic level, but the BSS138K is.
In the BSS138K data sheet, we see that the on resistance at a gate to source voltage of +3.3V is about 1.25 ohms. This is fairly close to fully on. If we use the same Panasonic relay as in the previous transistor circuit L1, the power dissipation is
P = ID^2 * RDSon
P = 0.01142 * 1.25 = 0.16 mW.
The data sheet says that the thermal resistance is 350C/W, so this part will operate with essentially no temperature rise.
For all practical purposes, the NMOS is a voltage driven device rather than current driven. There is no resistor shown between the GPIO pin and the gate. You may elsewhere see a series resistor placed here but typically this is not needed for small signal FETs if the trace from the GPIO to the gate is shorter that 5 or 10cm. If your PCB layout requires a longer run consider a 100 to 220 ohm resistor in series placed next to the GPIO pin. I do show a 47K resistor pull down to ground. The purpose of this is two fold. First, it makes sure that the NMOS is kept off when your board is powered on but before the microcontroller or PLD is programmed. If your boards are manufactured with pre-programmed parts you might not need it. FPGAs are re-configured at every power on and this ensures that the MOSFET remains off before reconfiguration. The other reason is that the GPIO may not output exactly 0V so it ensures that it is truly off.
L3) Very low voltage NMOS FET low side drive
This circuit is very similar to the previous one. If your GPIO voltage is lower than about +2.2V, even a logic level NMOS like the BSS138K will not fully turn on. The TI 2N7001TDCK level converter can be used to raise the gate drive voltage to 3.3V. Notice that it has two power supply connections, one to VCCIO and one to +3.3V. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
This circuit is very similar to the previous one. If your GPIO voltage is lower than about +2.2V, even a logic level NMOS like the BSS138K will not fully turn on. The TI 2N7001TDCK level converter can be used to raise the gate drive voltage to 3.3V. Notice that it has two power supply connections, one to VCCIO and one to +3.3V. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
L4) Low side peripheral driver
This circuit shows the use of a ULN2003B peripheral driver. This part was originally introduced by Sprague Electric back in the late 1970’s. It is now sold by TI, OnSemi, ST Micro, Diodes, and several others. It consists of seven open collector Darlington transistors and seven associated clamp diodes. A similar version with 8 transistors and diodes, the ULN2803 is also available with a different pin out. Each channel can switch 500mA but you must keep the total through the entire package to less than 2.5A. If you need more than 500mA, the channels can be paralleled by connecting the respective inputs and outputs together. The COM pin is not a power pin, rather it is the top side of internal clamp diodes. All of the transistor emitters are connected together through the E pin which must be connected to ground. Consult the ULN2003 data sheets for more information on how to use this part. Output a 0 from the GPIO and the load is off, output a 1 and the Darlington is on and the load is powered on.
This circuit shows the use of a ULN2003B peripheral driver. This part was originally introduced by Sprague Electric back in the late 1970’s. It is now sold by TI, OnSemi, ST Micro, Diodes, and several others. It consists of seven open collector Darlington transistors and seven associated clamp diodes. A similar version with 8 transistors and diodes, the ULN2803 is also available with a different pin out. Each channel can switch 500mA but you must keep the total through the entire package to less than 2.5A. If you need more than 500mA, the channels can be paralleled by connecting the respective inputs and outputs together. The COM pin is not a power pin, rather it is the top side of internal clamp diodes. All of the transistor emitters are connected together through the E pin which must be connected to ground. Consult the ULN2003 data sheets for more information on how to use this part. Output a 0 from the GPIO and the load is off, output a 1 and the Darlington is on and the load is powered on.
L5) Voltage translator drive of low side NMOS FET
The CMOS 4000B logic series has a voltage translator part, the TI CD4504B or the OnSemi MC14504B. This part contains 6 non-inverting buffers that can have their inputs powered by one voltage supply pin and their outputs powered by a second higher voltage supply pin. You can get up to 6 gate drive signals with this part. Each output can typically drive 6.8 mA at +15V. If you need to switch the load at a higher rate, you can parallel several level shift buffers together and get a higher current drive to better drive the capacitance of a typical higher power NMOS gate. The example circuit below shows two level shift buffer sections in parallel. The 4504B VCC pin is connected to the same VCCIO as the GPIO pin and the VDD pin is connected to a separate higher voltage of +5 to +15V as needed by the NMOS gate. The 4504B MODE pin should be connected to ground. The Nexperia HEF4104 is a similar part with 4 level shifting buffers and no MODE pin. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
The CMOS 4000B logic series has a voltage translator part, the TI CD4504B or the OnSemi MC14504B. This part contains 6 non-inverting buffers that can have their inputs powered by one voltage supply pin and their outputs powered by a second higher voltage supply pin. You can get up to 6 gate drive signals with this part. Each output can typically drive 6.8 mA at +15V. If you need to switch the load at a higher rate, you can parallel several level shift buffers together and get a higher current drive to better drive the capacitance of a typical higher power NMOS gate. The example circuit below shows two level shift buffer sections in parallel. The 4504B VCC pin is connected to the same VCCIO as the GPIO pin and the VDD pin is connected to a separate higher voltage of +5 to +15V as needed by the NMOS gate. The 4504B MODE pin should be connected to ground. The Nexperia HEF4104 is a similar part with 4 level shifting buffers and no MODE pin. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
L6) High speed gate drive of low side N MOSFET
This circuit shows the use of a high speed gate drive buffer from ST Micro. The PM8841 is intended to be used as a gate driver for PWM use. Notice the similar use of two separate power supply voltages, one at the VCCIO voltage and one at a higher voltage. The PM8841 is just one example, many others are available from many vendors. You may need to adjust the values of the two resistors shown as 10 ohms in the figure. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
This circuit shows the use of a high speed gate drive buffer from ST Micro. The PM8841 is intended to be used as a gate driver for PWM use. Notice the similar use of two separate power supply voltages, one at the VCCIO voltage and one at a higher voltage. The PM8841 is just one example, many others are available from many vendors. You may need to adjust the values of the two resistors shown as 10 ohms in the figure. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
High Side Driver Circuits
H1) High side drive – THE WRONG WAY
The first high side example below shows the wrong way to drive the high side switch. In the illustration, it shows an NPN transistor (or alternatively an NMOS FET) with the collector (drain) connected to a voltage the same or higher than the VCCIO and the emitter (source) connected to the top of the load. This configuration is called an emitter follower (source follower) and works well as a buffer amplifier. But it does not work as a saturated power switch. The reason is that for a transistor to be fully turned on, current must flow into the base and the only way for that to happen is if the GPIO pin is at a higher voltage than one diode drop above the emitter. For an NMOS to be fully turned on, the gate voltage must be at least VGSon higher than the source. Typically a PNP or PMOS is preferred as a high side switch. But see the high side examples H6 and H7 for some ways to use an NMOS as a high side switch.
H1) High side drive – THE WRONG WAY
The first high side example below shows the wrong way to drive the high side switch. In the illustration, it shows an NPN transistor (or alternatively an NMOS FET) with the collector (drain) connected to a voltage the same or higher than the VCCIO and the emitter (source) connected to the top of the load. This configuration is called an emitter follower (source follower) and works well as a buffer amplifier. But it does not work as a saturated power switch. The reason is that for a transistor to be fully turned on, current must flow into the base and the only way for that to happen is if the GPIO pin is at a higher voltage than one diode drop above the emitter. For an NMOS to be fully turned on, the gate voltage must be at least VGSon higher than the source. Typically a PNP or PMOS is preferred as a high side switch. But see the high side examples H6 and H7 for some ways to use an NMOS as a high side switch.
H2) Simple PNP transistor high side drive
This circuit is suitable for driving a small signal PNP switching transistor. The transistor emitter voltage must be the same as VCCIO. The design equations are similar to the low side drive example L1. Notice that this circuit can only drive very low voltage loads. Output a 1 from the GPIO and the load is off, output a 0 and the transistor is on and the load is powered on.
This circuit is suitable for driving a small signal PNP switching transistor. The transistor emitter voltage must be the same as VCCIO. The design equations are similar to the low side drive example L1. Notice that this circuit can only drive very low voltage loads. Output a 1 from the GPIO and the load is off, output a 0 and the transistor is on and the load is powered on.
H3) Simple PMOS FET high side drive
This circuit is suitable for driving a small signal PMOS FET switch. The PMOS source voltage must be the same as VCCIO. The design notes are similar to the low side drive example L2. But notice that this circuit can only drive very low voltage loads. Output a 1 from the GPIO and the load is off, output a 0 and the FET is on and the load is powered on.
This circuit is suitable for driving a small signal PMOS FET switch. The PMOS source voltage must be the same as VCCIO. The design notes are similar to the low side drive example L2. But notice that this circuit can only drive very low voltage loads. Output a 1 from the GPIO and the load is off, output a 0 and the FET is on and the load is powered on.
H4) Voltage translator drive of high side P MOSFET
This circuit uses the CMOS 4504B voltage translator part to translate the low voltage GPIO pin to up to a 0 to +15V swing. See the description of low side example L5 for more information on using this part. In this example, the input of the 4504B translator is powered by the same VCCIO as the GPIO and the output of the translator is powered by up to +15V. The source of the PMOS switch is connected to the higher voltage. In this circuit, the PMOS gate sees the full 0 to 15V range, so you need to make sure your part’s gate can can handle that voltage range. Output a 1 from the GPIO and the load is off, output a 0 and the PMOS is on and the load is powered on.
This circuit uses the CMOS 4504B voltage translator part to translate the low voltage GPIO pin to up to a 0 to +15V swing. See the description of low side example L5 for more information on using this part. In this example, the input of the 4504B translator is powered by the same VCCIO as the GPIO and the output of the translator is powered by up to +15V. The source of the PMOS switch is connected to the higher voltage. In this circuit, the PMOS gate sees the full 0 to 15V range, so you need to make sure your part’s gate can can handle that voltage range. Output a 1 from the GPIO and the load is off, output a 0 and the PMOS is on and the load is powered on.
H5) High voltage drive of high side PMOS FET
This circuit uses a small logic level NMOS and some resistors as a voltage translator to create a V+ referenced gate drive for the power PMOS device.
This circuit is suitable for selectively powering sections of your circuit on and off. For example, you might want to always keep the microcontroller powered on but be able to independently turn the power to a higher voltage motor controller on or off.
Output a 0 from the GPIO and the NMOS is off. It’s drain will then be at V+ and thus so will the PMOS gate. Output a 1 from the GPIO and the NMOS turns on and it’s drain will then be essentially at ground. I show the two drain resistor values as a 2:1 voltage divider. So the PMOS gate will now be at V+ / 2. If V+ is +24V, then when the NMOS is on, the PMOS gate will be at 24V - 12V = +12V. I show a 12V zener in parallel as protection to ensure that the PMOS gate doesn’t get to more than -12V from the source. Adjust the resistor ratios and the zener voltage for other gate voltages then the example shown here. A drawback of this circuit is that if you use lower value resistors, they will start to dissipate a good deal of power as heat. For a +24V supply, the resistor values shown in the drawing are probably about as small as you would want to go. You could reduce the power dissipated in the resistors by increasing their values at the expense of slower switching speed. In conclusion, output a 0 from the GPIO and the load is off, output a 1 and the PMOS is on and the load is powered on.
This circuit uses a small logic level NMOS and some resistors as a voltage translator to create a V+ referenced gate drive for the power PMOS device.
This circuit is suitable for selectively powering sections of your circuit on and off. For example, you might want to always keep the microcontroller powered on but be able to independently turn the power to a higher voltage motor controller on or off.
Output a 0 from the GPIO and the NMOS is off. It’s drain will then be at V+ and thus so will the PMOS gate. Output a 1 from the GPIO and the NMOS turns on and it’s drain will then be essentially at ground. I show the two drain resistor values as a 2:1 voltage divider. So the PMOS gate will now be at V+ / 2. If V+ is +24V, then when the NMOS is on, the PMOS gate will be at 24V - 12V = +12V. I show a 12V zener in parallel as protection to ensure that the PMOS gate doesn’t get to more than -12V from the source. Adjust the resistor ratios and the zener voltage for other gate voltages then the example shown here. A drawback of this circuit is that if you use lower value resistors, they will start to dissipate a good deal of power as heat. For a +24V supply, the resistor values shown in the drawing are probably about as small as you would want to go. You could reduce the power dissipated in the resistors by increasing their values at the expense of slower switching speed. In conclusion, output a 0 from the GPIO and the load is off, output a 1 and the PMOS is on and the load is powered on.
H6) Photovoltaic optocoupler drive of high side NMOS FET
This example circuit shows a way to use an NMOS device as a high side switch. Here a photovoltaic optoisolator is used as the NMOS gate drive. This type of isolator contains what are essentially a series of small solar cells. Drive the LED with current from the low voltage GPIO and the photovoltaic cell outputs a voltage. So if its negative output is connected to the NMOS source at the top of the load and its positive output to the NMOS gate, when current is passed through the LED, a voltage is generated that can be used to turn on the NMOS. Most of these devices output somewhere between +5V and +15V with 5 to 20mA of LED input current. Typically these are fairly slow devices, so you may not be able to PWM this configuration. A 1M (shown) to 10M resistor across the isolator output ensures that it drops back to 0V when the LED current is turned off. With a suitable NMOS, you may be able to control a good deal of power this way. Note that photovoltaic isolators are typically used to drive the NMOS devices inside solid state relays. In fact, this what is shown here is essentially the schematic of a DC type solid state relay. Several manufacturers of these isolators include Vishay, Panasonic, Toshiba, Infineon, and Broadcom. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
This example circuit shows a way to use an NMOS device as a high side switch. Here a photovoltaic optoisolator is used as the NMOS gate drive. This type of isolator contains what are essentially a series of small solar cells. Drive the LED with current from the low voltage GPIO and the photovoltaic cell outputs a voltage. So if its negative output is connected to the NMOS source at the top of the load and its positive output to the NMOS gate, when current is passed through the LED, a voltage is generated that can be used to turn on the NMOS. Most of these devices output somewhere between +5V and +15V with 5 to 20mA of LED input current. Typically these are fairly slow devices, so you may not be able to PWM this configuration. A 1M (shown) to 10M resistor across the isolator output ensures that it drops back to 0V when the LED current is turned off. With a suitable NMOS, you may be able to control a good deal of power this way. Note that photovoltaic isolators are typically used to drive the NMOS devices inside solid state relays. In fact, this what is shown here is essentially the schematic of a DC type solid state relay. Several manufacturers of these isolators include Vishay, Panasonic, Toshiba, Infineon, and Broadcom. Output a 0 from the GPIO and the load is off, output a 1 and the NMOS is on and the load is powered on.
H7) Charge pump drive of high side NMOS FET
This circuit shows another way to use an NMOS as a high side switch. As with the previous photovoltaic example, the idea is to make the voltage on the gate rise above the voltage of the source. This circuit shows a simple charge pump made up of a 0.1uF and a 1.0uF capacitor and two small signal Schottky diodes. Output a 0 from the GPIO and the NMOS is off, output a square wave of around 10kHz and the circuit will pump up to a positive voltage, thus turning the NMOS on. The parallel resistor is intended to drain the voltage charge stored on the 1.0 uF capacitor back to 0 when the GPIO turns back off. Its value is a tradeoff between turn off speed and sufficient gate drive voltage. This is a fairly slow process so you may not be able to PWM the power any faster than a few Hz with this circuit. Several IC vendors also make integrated versions of this concept to drive high side NFETs.
This circuit shows another way to use an NMOS as a high side switch. As with the previous photovoltaic example, the idea is to make the voltage on the gate rise above the voltage of the source. This circuit shows a simple charge pump made up of a 0.1uF and a 1.0uF capacitor and two small signal Schottky diodes. Output a 0 from the GPIO and the NMOS is off, output a square wave of around 10kHz and the circuit will pump up to a positive voltage, thus turning the NMOS on. The parallel resistor is intended to drain the voltage charge stored on the 1.0 uF capacitor back to 0 when the GPIO turns back off. Its value is a tradeoff between turn off speed and sufficient gate drive voltage. This is a fairly slow process so you may not be able to PWM the power any faster than a few Hz with this circuit. Several IC vendors also make integrated versions of this concept to drive high side NFETs.
Conclusions
Several different methods of low side and high side drive of power devices from a microcontroller or PLD GPIO pin have been presented. Each method involves a trade-off in one way or another. Be sure to make a hand built prototype before committing any of these suggestions to a PCB design. Good luck!
8-May-2020
Several different methods of low side and high side drive of power devices from a microcontroller or PLD GPIO pin have been presented. Each method involves a trade-off in one way or another. Be sure to make a hand built prototype before committing any of these suggestions to a PCB design. Good luck!
8-May-2020
Analog Design Ideas
Coming soon!
Coming soon!
Copyright 2019 -2022 ElectroLuck