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Graphic library of CMOS 4000 series parts for use with Intel/Altera Quartus Prime
Back in the early days of FPGA’s and CPLD’s, design was often done with schematics. Altera's Maxplus II provided a library of graphic “Primitives” and a library of graphic “Old-Style Macrofunctions”. The Primitives library consisted of basic building block components such as inverters, gates, flip flops, and I/O pins. The Old-Style Macrofunctions library consisted of a good majority of the 7400 TTL catalog along with a few other things. This was back in the day when Altera was trying to convince designers to give up their discrete logic and move to FPGA/CPLD design while the TTL catalog was still familiar to everyone. Most TTL datasheets present the internal schematic of the part so it was fairly easy to re-create their functionality in the programmable world.
Around 2000, I was doing several projects that needed the functionality found in several CMOS 4000 series parts that were not in the 7400 catalog. So using the internal schematics found in the CMOS 4000 data sheets, I created a few of these macrofunctions. Over the next few years during down times between consulting projects, I started to build more 4000 parts and at some point I decided to make it into a full library. It then occupied various hard drives and backups for 15 years. Recently I decided to revive this library and convert it to Intel Quartus Prime format. The Maxplus II files were in .GDF format for the internal designs and .SYM format for the top level symbols. Luckily Quartus Prime can read these old file formats and save them back out in a modern format. The .GDF files become .BDF (block design file) format and the .SYM files become .BSF (block symbol file) format.
This library contains graphic macrofunctions based on the classic 4000 series of CMOS logic parts - CD4000 (RCA/GE/Intersil/Harris/TI and NSC/Fairchild/TI), HEF4000 (Philips/NXP/Nexperia), MC14000 (Motorola/OnSemi), HCF/HCC4000 (STMicro), and TC4000 (Toshiba). The library is in the same spirit as Altera's library of “Old-Style Macrofunctions” that is based on the 7400 series of TTL logic parts. Today you would typically design an FPGA with VHDL/Verilog/SystemVerilog but there could be times, especially when converting legacy designs, when using a known macrofunction and a schematic might get you to a result faster and easier. Over 100 different CMOS 4000 logic parts are represented in the library ranging from simple buffers and gates to counters, encoders, decoders, shift registers, and BCD display drivers - and from the currently available to the discontinued. Generally not included in the library are those parts that contain some form of analog functionality such as analog switches, oscillators, monostables, and logic level shifters.
Here are a few example symbols:
Back in the early days of FPGA’s and CPLD’s, design was often done with schematics. Altera's Maxplus II provided a library of graphic “Primitives” and a library of graphic “Old-Style Macrofunctions”. The Primitives library consisted of basic building block components such as inverters, gates, flip flops, and I/O pins. The Old-Style Macrofunctions library consisted of a good majority of the 7400 TTL catalog along with a few other things. This was back in the day when Altera was trying to convince designers to give up their discrete logic and move to FPGA/CPLD design while the TTL catalog was still familiar to everyone. Most TTL datasheets present the internal schematic of the part so it was fairly easy to re-create their functionality in the programmable world.
Around 2000, I was doing several projects that needed the functionality found in several CMOS 4000 series parts that were not in the 7400 catalog. So using the internal schematics found in the CMOS 4000 data sheets, I created a few of these macrofunctions. Over the next few years during down times between consulting projects, I started to build more 4000 parts and at some point I decided to make it into a full library. It then occupied various hard drives and backups for 15 years. Recently I decided to revive this library and convert it to Intel Quartus Prime format. The Maxplus II files were in .GDF format for the internal designs and .SYM format for the top level symbols. Luckily Quartus Prime can read these old file formats and save them back out in a modern format. The .GDF files become .BDF (block design file) format and the .SYM files become .BSF (block symbol file) format.
This library contains graphic macrofunctions based on the classic 4000 series of CMOS logic parts - CD4000 (RCA/GE/Intersil/Harris/TI and NSC/Fairchild/TI), HEF4000 (Philips/NXP/Nexperia), MC14000 (Motorola/OnSemi), HCF/HCC4000 (STMicro), and TC4000 (Toshiba). The library is in the same spirit as Altera's library of “Old-Style Macrofunctions” that is based on the 7400 series of TTL logic parts. Today you would typically design an FPGA with VHDL/Verilog/SystemVerilog but there could be times, especially when converting legacy designs, when using a known macrofunction and a schematic might get you to a result faster and easier. Over 100 different CMOS 4000 logic parts are represented in the library ranging from simple buffers and gates to counters, encoders, decoders, shift registers, and BCD display drivers - and from the currently available to the discontinued. Generally not included in the library are those parts that contain some form of analog functionality such as analog switches, oscillators, monostables, and logic level shifters.
Here are a few example symbols:
After some 50 years of production, the CMOS 4000 parts are useful and are still mass produced by at least 5 major semiconductor manufacturers. Some of the more obscure parts are slowly being obsoleted but their function is captured in the C4000 library.
Interestingly, Intel/Altera still provides the Old-Style Macrofunction library even with the latest version of Quartus Prime. So they must still be useful to some designers. I hope that the ElectroLuck C4000 library will be similarly useful to designers.
Here is a tip. When designing with any of these graphic macrofunction libraries, it is very useful to be able to simulate and verify your design before committing for to download it to your hardware. With VHDL/Verilog/SystemVerilog, you would probably simulate and verify with ModelSim or Questa. Up through version 9.1, Quartus had its own internal ability to simulate your designs. You created stimulus vector waveform files (.VWF), compiled your design and the Simulator could then either perform a functional or a timing accurate simulation. These VWF files are graphical and a bit different than VHDL or Verilog test benches because they can't interact with the logic design. They are just provide simple stimulus. But many times, that's all you need. After version 9.1, this capability was eliminated from Quartus. Unfortunately, you can't download version 9.1 from the Intel website anymore so that option is gone. I think that EE schools complained about this to Intel, because they sort of re-introduced the capability sometime around Quartus version 13. It's a bit cranky, it uses the same waveform editor interface that was used in versions up to 9.1, but instead of using the internal Altera simulator, it compiles the waveform into a test bench that runs with ModelSim. Then the ModelSim output is passed back to the Quartus waveform editor interface. The caveat here is that these are usually functional simulations, and not timing accurate ones. Timing simulations are only available for select devices. And the second caveat is that you can only simulate for a short timespan. This capability is part of Quartus' "University Program" and finding it is kind of an Easter egg hunt. In Quartus Prime, click file > New > Verification/Debugging Files > University Program VWF. You could also search the internet for the Intel tutorial document called "Introduction to Simulation of VHDL Designs". Other tutorials are also available online. The VWF will also work with Verilog and schematic BDF designs.
The C4000 ZIP file contains the .BDF and .BSF files, a VHDL package file, documentation, and some example designs. Get the C4000 library here:
Interestingly, Intel/Altera still provides the Old-Style Macrofunction library even with the latest version of Quartus Prime. So they must still be useful to some designers. I hope that the ElectroLuck C4000 library will be similarly useful to designers.
Here is a tip. When designing with any of these graphic macrofunction libraries, it is very useful to be able to simulate and verify your design before committing for to download it to your hardware. With VHDL/Verilog/SystemVerilog, you would probably simulate and verify with ModelSim or Questa. Up through version 9.1, Quartus had its own internal ability to simulate your designs. You created stimulus vector waveform files (.VWF), compiled your design and the Simulator could then either perform a functional or a timing accurate simulation. These VWF files are graphical and a bit different than VHDL or Verilog test benches because they can't interact with the logic design. They are just provide simple stimulus. But many times, that's all you need. After version 9.1, this capability was eliminated from Quartus. Unfortunately, you can't download version 9.1 from the Intel website anymore so that option is gone. I think that EE schools complained about this to Intel, because they sort of re-introduced the capability sometime around Quartus version 13. It's a bit cranky, it uses the same waveform editor interface that was used in versions up to 9.1, but instead of using the internal Altera simulator, it compiles the waveform into a test bench that runs with ModelSim. Then the ModelSim output is passed back to the Quartus waveform editor interface. The caveat here is that these are usually functional simulations, and not timing accurate ones. Timing simulations are only available for select devices. And the second caveat is that you can only simulate for a short timespan. This capability is part of Quartus' "University Program" and finding it is kind of an Easter egg hunt. In Quartus Prime, click file > New > Verification/Debugging Files > University Program VWF. You could also search the internet for the Intel tutorial document called "Introduction to Simulation of VHDL Designs". Other tutorials are also available online. The VWF will also work with Verilog and schematic BDF designs.
The C4000 ZIP file contains the .BDF and .BSF files, a VHDL package file, documentation, and some example designs. Get the C4000 library here:
| c4000_library_rev000.zip |
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20-March-2020, revised 8-May-2022
20-March-2020, revised 8-May-2022
Bit Serial Arithmetic in FPGAs and CPLDs
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